|
EETimes
Startup claims single-clock I/O technology
Nicolas Mokhoff
WirelessNet DesignLine
SerDes: A new definition?
Jack Shandle
EDN
High-speed serial I/O as SoC interconnect: an evolution
Ron Wilson
PLDesignLine
How to turn every FPGA LVDS pair into a complete SERDES solution
Clive "Max" Maxfield
Embedded Systems Conference News
Embedded.com
SerDes on the cheap
Kenton Williston
SoCcentral
Align Engineering Lock Loop
Ensures Single-Clock Domain
SoCentral |